1. Technical Field
The embodiments described herein relate to a DFLOP circuit, and in particular, to a DFLOP circuit that is used in an EAIC (Externally asynchronous-internally clocked) system, which internally generates a clock signal in an asynchronous system.
2. Related Art
Recently, restrictions inherent in conventional asynchronous circuits and new challenges for timing detection present by conventional semiconductor devices, a system that externally operates in an asynchronous manner but internally operates based on a clock signal, that is in a synchronous manner, has been introduced. Such a system is called an EAIC (Externally Asynchronous-Internally Clocked) system. In an EAIC system, when viewed from outside the device, only an external output signal, which responds to an external input signal, seems to be present, but actually an internal clock signal is generated on the basis of the input signal.
A DFLOP is used for a shift register in the EAIC system. FIGS. 1 and 2 are a conceptual view and a block diagram of a conventional DFLOP. The DFLOP of FIGS. 1 and 2 operates similarly to a D flip-flop, except that if a signal transmission operation is completed, then a ready signal R is generated to inform that the DFLOP is ready to execute a new operation.
Referring to FIGS. 1 and 2, the DFLOP includes a resolver 10, a metastable detection stage (MDS) 20, a latch 30, and a ready signal generator 40.
First, the resolver 10 is a flip-flop type logic for defining operation conditions according to an input signal. The resolver 10 receives an input signal ‘in’ and an internally generated internal clock signal ‘CLK’, and generates first output signals ‘Y0’ and ‘Y1’. Specifically, if the internal clock signal ‘CLK’ is at a low level, then the resolver 10 generates the first output signals ‘Y0’ and ‘Y1’ at high level, regardless of the input signal ‘in’. When the internal clock signal ‘CLK’ is changed to a high level, then the resolver 10 generates the first output signals ‘Y0’ and ‘Y1’ according to the input signal ‘in’. The detailed structure and operation of the resolver 10 will be described below.
The MDS 20 generates second output signals ‘Y0′’ and ‘Y1′’ in response to the first output signals ‘Y0’ and ‘Y1’. The MDS 20 functions to remove metastable components in the input signals. That is, the first output signals ‘Y0’ and ‘Y1’ are not provided as the second output signals ‘Y0′’ and ‘Y1′’ until after they are completely changed, for example, from low level to high level. Accordingly, the logic is implemented such that the signals are transmitted after the levels of the input signals are completely changed, thereby removing the metastable states of the output signals.
The latch 30 receives the second output signals ‘Y0′’ and ‘Y1′’, and supplies final output signals ‘Q’ and ‘/Q’. The latch 30 includes, for example, an RS flip-flop. If the latch 30 includes, e.g., a NOR type RS flip-flop, then the latch 30 operates in response to an input signal at a high level. Meanwhile, if the latch 30 includes, e.g., a NAND type RS flip-flop, then the latch 30 operates in response to an input signal at a low level. These may be selectively used depending on the purpose or structure of the DFLOP, and thus the general concept of the latch 30 will be described briefly herein.
The DFLOP further includes a ready signal generator 40. The ready signal generator 40 generates the ready signal ‘R’ on the basis of the second output signals ‘Y0′’ and ‘Y1′’ from the MDS 20. As described above, the ready signal ‘R’ informs that signal transmission is completed and it is ready to execute a next operation. The ready signal generator 40 includes a NAND gate ND that performs a NAND operation on the second output signals ‘Y0′’ and ‘Y1′’ to output the ready signal ‘R’.
As such, in the DFLOP 1, the MDS 20 generates the ready signal ‘R’ after the signals are transmitted from the resolver 10. Accordingly, the metastable state can be excluded, and an internal stable operation can be implemented. In addition, the internal clock signal ‘CLK’ may be generated by combining the ready signals ‘R’ output from the DFLOP 1.
FIG. 3 is a circuit diagram of the resolver 10 shown in FIG. 2. Referring to FIG. 3, the resolver 10 includes an inverter IV1 and first to fourth NAND gates ND1 to ND4.
An input signal ‘D’ and an inverted signal of the input signal D generated by the inverter IV1 are supplied to the fourth NAND gate ND4 and the first NAND gate ND1, respectively.
The second and third NAND gates ND2 and ND3 receive the internal clock signal ‘CLK’ and are fed back with the output signals from the first and fourth NAND gates ND1 and ND4, respectively. Then, the second and third NAND gates ND2 and ND3 perform a NAND gate operation and supply the first output signals ‘Y1’ and ‘Y0’, respectively.
During the operation, when the internal clock signal ‘CLK’ is at a low level, the resolver 10 supplies the deactivated first output signals ‘Y0’ and ‘Y1’ at a high level. Then, if the internal clock signal ‘CLK’ is changed to a high level, then the resolver 10 supplies the first output signals ‘Y0’ and ‘Y1’ according to the input signal ‘D’. For example, if the internal clock signal ‘CLK’ is at a high level and the input signal ‘D’ is at a high level, then the first positive output signal ‘Y0’ transitions to a low level opposite to the input signal D, and the first negative output signal ‘Y1’ transitions to a high level opposite to the first positive output signal ‘Y0’. Meanwhile, if the internal clock signal ‘CLK’ is at a high level and the input signal ‘D’ is at a low level, then the first positive output signal ‘Y0’ transitions to a high level opposite to the input signal ‘D’, and the first negative output signal ‘Y1’ transitions to a low level opposite to the first positive output signal Y0.
However, for the resolver 10, the three-input NAND gates ND2 and ND3, the two-input NAND gates ND1 and ND4, and the inverter IV1 are needed. Specifically, since 11 PMOS transistors and 11 NMOS transistors are needed, the layout efficiency is poor. In addition, the response speed may be lowered due to the NAND gate operations with the feedback inputs.